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・ Cray MTA-2
・ Cray Operating System
・ Cray Plaza
・ Cray Reservoir
・ Cray S-MP
・ Cray SV1
・ Cray T3D
・ Cray T3E
・ Cray T90
・ Cray Time Sharing System
・ Cray Urika-GD
・ Cray Urika-XA
・ Cray Valley Paper Mills F.C.
・ Cray Wanderers F.C.
・ Cray X-MP
Cray X1
・ Cray X2
・ Cray XC30
・ Cray XC40
・ Cray XD1
・ Cray XE6
・ Cray XK6
・ Cray XK7
・ Cray XMS
・ Cray XMT
・ Cray XT3
・ Cray XT4
・ Cray XT5
・ Cray XT6
・ Cray Y-MP


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Cray X1 : ウィキペディア英語版
Cray X1

The Cray X1 is a non-uniform memory access, vector processor supercomputer manufactured and sold by Cray Inc. since 2003. The X1 is often described as the unification of the Cray T90, Cray SV1, and Cray T3E architectures into a single machine. The X1 shares the multistreaming processors, vector caches, and CMOS design of the SV1, the highly scalable distributed memory design of the T3E, and the high memory bandwidth and liquid cooling of the T90.
The X1 uses a 1.2 ns (800 MHz) clock cycle, and 8-wide vector pipes in MSP mode, offering a peak speed of 12.8 gigaflops per processor. Air-cooled models are available with up to 64 processors. Liquid-cooled systems scale to a theoretical maximum of 4096 processors, comprising 1024 shared-memory nodes connected in a two-dimensional torus network, in 32 frames. Such a system would supply a peak speed of 50 teraflops. The largest unclassified X1 system was the 512 processor system at Oak Ridge National Laboratory, though this has since been upgraded to an X1E system.
The X1 can be programmed either with widely used message passing software like MPI and PVM, or with shared-memory languages like Unified Parallel C programming language or Co-array Fortran. The X1 runs an operating system called UNICOS/mp which shares more with the SGI IRIX operating system than it does with the UNICOS found on prior generation Cray machines.
In 2005, Cray released the X1E upgrade, which uses dual-core processors, allowing two quad-processor nodes to fit on a node board. The processors are also upgraded to 1150 MHz. This upgrade almost triples the peak performance per board, but reduces the per-processor memory and interconnect bandwidth. X1 and X1E boards can be combined within the same system.
The X1 is notable for its development being partly funded by United States
Government's National Security Agency (under the code name
SV2).〔(NSA Secures Future of Cray SV2 With 5-Year Funding Deal )〕
The X1 was not a financially successful product〔(Cray Inc. 10k-filing for December 31, 2005 )〕 and it seems doubtful that it
or its successors would have been produced without this support.
==References==


抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
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